NXP Semiconductors /MIMXRT1064 /SystemControl /CLIDR

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Interpret as CLIDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CL1_0)CL10 (CL2_0)CL20 (CL3_0)CL30 (CL4_0)CL40 (CL5_0)CL50 (CL6_0)CL60 (CL7_0)CL70 (LOUIS_0)LOUIS0 (LOC_0)LOC0 (LOU_0)LOU

CL1=CL1_0, CL2=CL2_0, CL7=CL7_0, CL3=CL3_0, LOC=LOC_0, CL4=CL4_0, LOU=LOU_0, LOUIS=LOUIS_0, CL5=CL5_0, CL6=CL6_0

Description

Cache Level ID register

Fields

CL1

Indicate the type of cache implemented at level 1.

0 (CL1_0): No cache

1 (CL1_1): Instruction cache only

2 (CL1_2): Data cache only

3 (CL1_3): Separate instruction and data caches

4 (CL1_4): Unified cache

CL2

Indicate the type of cache implemented at level 2.

0 (CL2_0): No cache

1 (CL2_1): Instruction cache only

2 (CL2_2): Data cache only

3 (CL2_3): Separate instruction and data caches

4 (CL2_4): Unified cache

CL3

Indicate the type of cache implemented at level 3.

0 (CL3_0): No cache

1 (CL3_1): Instruction cache only

2 (CL3_2): Data cache only

3 (CL3_3): Separate instruction and data caches

4 (CL3_4): Unified cache

CL4

Indicate the type of cache implemented at level 4.

0 (CL4_0): No cache

1 (CL4_1): Instruction cache only

2 (CL4_2): Data cache only

3 (CL4_3): Separate instruction and data caches

4 (CL4_4): Unified cache

CL5

Indicate the type of cache implemented at level 5.

0 (CL5_0): No cache

1 (CL5_1): Instruction cache only

2 (CL5_2): Data cache only

3 (CL5_3): Separate instruction and data caches

4 (CL5_4): Unified cache

CL6

Indicate the type of cache implemented at level 6.

0 (CL6_0): No cache

1 (CL6_1): Instruction cache only

2 (CL6_2): Data cache only

3 (CL6_3): Separate instruction and data caches

4 (CL6_4): Unified cache

CL7

Indicate the type of cache implemented at level 7.

0 (CL7_0): No cache

1 (CL7_1): Instruction cache only

2 (CL7_2): Data cache only

3 (CL7_3): Separate instruction and data caches

4 (CL7_4): Unified cache

LOUIS

Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ.

0 (LOUIS_0): 0

1 (LOUIS_1): 1

2 (LOUIS_2): 2

3 (LOUIS_3): 3

4 (LOUIS_4): 4

5 (LOUIS_5): 5

6 (LOUIS_6): 6

7 (LOUIS_7): 7

LOC

Level of Coherency for the cache hierarchy

0 (LOC_0): 0

1 (LOC_1): 1

2 (LOC_2): 2

3 (LOC_3): 3

4 (LOC_4): 4

5 (LOC_5): 5

6 (LOC_6): 6

7 (LOC_7): 7

LOU

Level of Unification for the cache hierarchy

0 (LOU_0): 0

1 (LOU_1): 1

2 (LOU_2): 2

3 (LOU_3): 3

4 (LOU_4): 4

5 (LOU_5): 5

6 (LOU_6): 6

7 (LOU_7): 7

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